A 12-bit 50M samples/s digitally self-calibrated pipelined ADC
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The Department of Electrical and Computer Engineering (ECpE) contains two focuses. The focus on Electrical Engineering teaches students in the fields of control systems, electromagnetics and non-destructive evaluation, microelectronics, electric power & energy systems, and the like. The Computer Engineering focus teaches in the fields of software systems, embedded systems, networking, information security, computer architecture, etc.
History
The Department of Electrical Engineering was formed in 1909 from the division of the Department of Physics and Electrical Engineering. In 1985 its name changed to Department of Electrical Engineering and Computer Engineering. In 1995 it became the Department of Electrical and Computer Engineering.
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1909-present
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- Department of Electrical Engineering (1909-1985)
- Department of Electrical Engineering and Computer Engineering (1985-1995)
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- College of Engineering (parent college)
- Department of Physics and Electrical Engineering (predecessor)
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Abstract
This thesis describes the different aspects of the design and implementation of a 12-bit 50M samples/s pipelined non-binary radix 1.9 analog-to-digital converter. The converter architecture is made up of 14 stages with an interstage gain of 1.9 (non-binary radix). Each stage is made of one fully differential sample-and-hold amplifier (SHA), a 1-bit sub-ADC (basically one comparator) and a 1-bit DAC. The sub-DAC functionality is rolled in as part of the SHA switch capacitor architecture which is referred to as the multiplying DAC (MDAC). The self-calibration function is performed in a cyclical fashion and the entire pipeline is used to perform the calibration for each stage. The settling time on the MDAC is about 9ns with a gain of approximately 8ldB. The entire pipeline has been implemented in a digital 0.35[Mu]m CMOS process.