Degree Type

Thesis

Date of Award

1998

Degree Name

Master of Science

Department

Electrical and Computer Engineering

Abstract

This thesis describes the different aspects of the design and implementation of a 12-bit 50M samples/s pipelined non-binary radix 1.9 analog-to-digital converter. The converter architecture is made up of 14 stages with an interstage gain of 1.9 (non-binary radix). Each stage is made of one fully differential sample-and-hold amplifier (SHA), a 1-bit sub-ADC (basically one comparator) and a 1-bit DAC. The sub-DAC functionality is rolled in as part of the SHA switch capacitor architecture which is referred to as the multiplying DAC (MDAC). The self-calibration function is performed in a cyclical fashion and the entire pipeline is used to perform the calibration for each stage. The settling time on the MDAC is about 9ns with a gain of approximately 8ldB. The entire pipeline has been implemented in a digital 0.35[Mu]m CMOS process.

Publisher

Digital Repository @ Iowa State University, http://lib.dr.iastate.edu/

Copyright Owner

Xiaohong Du

Language

en

OCLC Number

40045392

File Format

application/pdf

File Size

79 pages

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