Campus Units

Aerospace Engineering, Computer Science, Electrical and Computer Engineering, Mathematics, Virtual Reality Applications Center

Document Type

Conference Proceeding

Conference

2020 Formal Methods in Computer Aided Design (FMCAD)

Publication Version

Published Version

Publication Date

12-22-2020

Journal or Book Title

Proceedings of the 20th International Conference on Formal Methods in Computer Aided Design

First Page

16

Last Page

25

DOI

10.34727/2020/isbn.978-3-85448-042-6_8

Conference Title

20th International Conference on Formal Methods in Computer Aided Design

Conference Date

September 21-24, 2020

Abstract

Industrial hardware verification tasks often require checking a large number of properties within a testbench. Verification tools often utilize parallelism in their solving orchestration to improve scalability, either in portfolio mode where different solver strategies run concurrently, or in partitioning mode where disjoint property subsets are verified independently. While most tools focus solely upon reducing end-to-end walltime, reducing overall CPU-time is a comparably-important goal influencing power consumption, competition for available machines, and IT costs. Portfolio approaches often degrade into highly-redundant work across processes, where similar strategies address properties in nearly-identical order. Partitioning should take property affinity into account, atomically verifying high-affinity properties to minimize redundant work of applying identical strategies on individual properties with nearly-identical logic cones. In this paper, we improve multi-property parallel verification with respect to both wall- and CPU-time. We extend affinity-based partitioning to guarantee complete utilization of available processes, with provable partition quality. We propose methods to minimize redundant computation, and dynamically optimize work distribution. We deploy our techniques in a sequential redundancy removal framework, using localization to solve non-inductive properties. Our techniques offer a median 2.4× speedup yielding 18.1% more property solves, as demonstrated by extensive experiments.

Comments

This proceeding is published as Dureja, Rohit, Jason Baumgartner, Robert Kanzelman, Mark Williams, and Kristin Y. Rozier. "Accelerating Parallel Verification via Complementary Property Partitioning and Strategy Exploration." In Proceedings of the 20th International Conference on Formal Methods in Computer Aided Design (Strichman, O. and A. Ivrii, eds.) (2020): 16-25. DOI: 10.34727/2020/isbn.978-3-85448-042-6_8. Posted with permission.

Creative Commons License

Creative Commons Attribution 4.0 International License
This work is licensed under a Creative Commons Attribution 4.0 International License.

Copyright Owner

IEEE

Language

en

File Format

application/pdf

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