Superscalar Processor Performance Enhancement through Reliable Dynamic Clock Frequency Tuning
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The Department of Electrical and Computer Engineering (ECpE) contains two focuses. The focus on Electrical Engineering teaches students in the fields of control systems, electromagnetics and non-destructive evaluation, microelectronics, electric power & energy systems, and the like. The Computer Engineering focus teaches in the fields of software systems, embedded systems, networking, information security, computer architecture, etc.
History
The Department of Electrical Engineering was formed in 1909 from the division of the Department of Physics and Electrical Engineering. In 1985 its name changed to Department of Electrical Engineering and Computer Engineering. In 1995 it became the Department of Electrical and Computer Engineering.
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1909-present
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- Department of Electrical Engineering (1909-1985)
- Department of Electrical Engineering and Computer Engineering (1985-1995)
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- College of Engineering (parent college)
- Department of Physics and Electrical Engineering (predecessor)
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Abstract
Synchronous circuits are typically clocked considering worst case timing paths so that timing errors are avoided under all circumstances. In the case of a pipelined processor, this has special implications since the operating frequency of the entire pipeline is limited by the slowest stage. Our goal, in this paper, is to achieve higher performance in superscalar processors by dynamically varying the operating frequency during run time past worst case limits. The key objective is to see the effect of overclocking on superscalar processors for various benchmark applications, and analyze the associated overhead, in terms of extra hardware and error recovery penalty, when the clock frequency is adjusted dynamically. We tolerate timing errors occurring at speeds higher than what the circuit is designed to operate at by implementing an efficient error detection and recovery mechanism. We also study the limitations imposed by minimum path constraints on our technique. Experimental results show that an average performance gain up to 57% across all benchmark applications is achievable.
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This is a manuscript of a proceeding published as Subramanian, Viswanathan, Mikel Bezdek, Naga D. Avirneni, and Arun Somani. "Superscalar processor performance enhancement through reliable dynamic clock frequency tuning." In 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07), (2007): 196-205. DOI: 10.1109/DSN.2007.90. Posted with permission.