This research focused on the development of a p-well CMOS fabrication process that has fast turnaround time, is relatively inexpensive, and is easy to use. Most current CMOS fabrication processes use either n-well or twin-well techniques in order to provide better device isolation and improved circuit performance. However, these processes suffer the disadvantages of being very complex and requiring high levels of control for most of the steps. An alternative route is to use a p-well process, which has the attractive characteristics of process simplicity, making it viable for use in an undergraduate laboratory setting. This project has focused on the development of a p-well process that could be implemented in the teaching laboratories at Microelectronics Research Center at ISU. The development included the design and fabrication the photomasks that define the transistor patterns and the design and development of the process sequence for building simple CMOS integrated circuits. After a series of development runs, working CMOS devices were achieved. The fabricated transistors had a gate oxide layer thickness of 350Å. Transistor width/length ratios were 10 [mu]m/5 [mu]m, 20 [mu]m/5 [mu]m, 40 [mu]m/5 [mu]m, 20 [mu]m/10 [mu]m, 40 [mu]m/10 [mu]m, and 80 [mu]m/10 [mu]m. A single layer of metal interconnects was used. Test structures and some simple demonstration circuits (inverters and gates) were included in the fabrication. The devices and circuits worked as expected, and the performance was relatively uniform over different wafers. NMOS transistors had the average threshold voltage are about 2.12 Volts, a field effect mobility of 220 cm2/Vs, and an early voltage of 325 Volts. On the other hand, the values for PMOS are -1.15 Volts, 250 cm2/Vs, and 84.62 Volts respectively.