Given the significant advantages of reprogrammable logic devices in terms of cost and design flexibility, considerable interest has arisen in the nuclear physics community regarding their feasibility for implementation in on-detector electronics. However, given the fact that such devices carry the drawback of being susceptible to radiation-induced bit upsets and other failures, considerable study is warranted as to their expected failure rate when placed in the radiation-hostile environments of nuclear physics experiments. In this thesis I propose a model which can be used to calculate expected upset rates in Xilinx's line radiation-hardened field programmable gate array (FPGA) offerings for the radiation environment at the PHENIX experiment on the Relativistic Heavy Ion Collider (RHIC) at Brookhaven National Laboratory. The results of this model are compared to an experiment carried out in March of 2004 in the PHENIX interaction region (IR), where actual upset data was obtained. With respect to this end, an overview of the experimental setup is given, along with a detailed description of the GEANT-based PISA model used for calculating the expected upset rate. In addition, a summary of the physical causes of upsets in SRAM-based devices and appropriate mitigation strategies is also given. The ultimate goal of such a model is to provide a versatile means of characterizing the radiation dose upon a proposed device anywhere within the PHENIX IR and accordingly estimating the expected device performance, in terms of both usable lifetime from total ionizing dose (TID) and the expected single event upset (SEU) rate. To evaluate the soundness of such a model in characterizing the radiation dose as a function of position within the PHENIX interaction region, the human-equivalent doses were calculated in the tested configurations and compared to actual results measured by dosimetry badges placed in the PHENIX IR. The resulting model can then be applied to create a model of the radiation environment in PHENIX, and specifically as a means of generating an upset profile as a function of integrated luminosity for specific SRAM-based devices whose bit upset profiles are known, such as with Xilinx's line of radiation-hardened FPGAs.