2010 IEEE 31st Real-Time Systems Symposium (RTSS)
Journal or Book Title
2010 31st IEEE Real-Time Systems Symposium
Nov. 30-Dec. 3, 2010
San Diego, CA
As demand for computational power of embedded applications has increased, their architectures have become more complex. One result of this increased complexity are real-time embedded systems with set-associative multi-level caches. Multi-level caches complicate the process of program analysis techniques such as worst case execution time (WCET). To address this need we have developed a sound cache behavior analysis that handles multi-level instruction and data caches. Our technique relies on a new abstraction, live caches, which models relationships between cache levels to improve accuracy. Our analysis improves upon previous multi-level cache analysis in three ways. First, it handles write-back, a common feature of cache models, soundly. Second, it handles both instruction and data cache hierarchies, and third, it improves precision of cache analysis. For standard WCET benchmarks and a multi-level cache configuration analyzed by previous work, we observed that live caches improve WCET precision resulting in an average of 6.3% reduction in computed WCET.
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Sondag, Tyler and Rajan, Hridesh, "A More Precise Abstract Domain for Multi-level Caches for Tighter WCET Analysis" (2010). Computer Science Conference Presentations, Posters and Proceedings. 22.