Publication Date

10-31-1992

Technical Report Number

TR92-15

Subjects

Computing Methodologies, Data, Information Systems, Hardware

Abstract

Hardware-assisted garbage collection combines the potential of high average-case allocation rates and memory bandwidth with fast worst-case allocation, fetch, and store times. This paper describes an architecture that allows memory fetch and store operations to execute, on the average, nearly as fast as traditional memory. Support for caching garbage-collected memory cells and a protocol designed to minimize communication between the CPU's cache and memory allow the system to deliver very high performance. The architecture is real-time in that the worst-case time required for a memory fetch or store is approximately six traditional memory cycles, and the time required to allocate an object is bounded by a small constant times the size of the object. A prototype of the proposed architecture has been successfully simulated. Continuing research focuses on measuring the system's performance under real workloads.

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