Campus Units

Electrical and Computer Engineering

Document Type

Conference Proceeding

Conference

FPGA08: ACM/SIGDA International Symposium on Field Programmable Gate Arrays

Publication Version

Accepted Manuscript

Link to Published Version

https://doi.org/10.1145/1344671.1344679

Publication Date

2-2008

Journal or Book Title

FPGA '08: Proceedings of the 16th international ACM/SIGDA symposium on Field Programmable Gate Arrays

First Page

37

Last Page

46

DOI

10.1145/1344671.1344679

Conference Title

FPGA08: ACM/SIGDA International Symposium on Field Programmable Gate Arrays

Conference Date

February 24-26, 2008

City

Monterey, CA

Abstract

Look-up table based FPGAs have migrated from a niche technology for design prototyping to a valuable end-product component and, in some cases, a replacement for general purpose processors and ASICs alike. One way architects have bridged the performance gap between FPGAs and ASICs is through the inclusion of specialized components such as multipliers, RAM modules, and microcontrollers. Another dedicated structure that has become standard in reconfigurable fabrics is the arithmetic carry chain. Currently, it is only used to map arithmetic operations as identified by HDL macros. For non-arithmetic operations, it is an idle but potentially powerful resource.

This work presents ChainMap, a polynomial-time delay-optimal technology mapping algorithm for the creation of generic logic chains in LUT-based FPGAs. ChainMap requires no HDL macros be preserved through the design flow. It creates logic chains, both arithmetic and non-arithmetic, in an arbitrary Boolean network whenever depth increasing nodes are encountered. Use of the chain is not reserved for arithmetic, but rather any set of gates exhibiting similar characteristics. By using the carry chain as a generic, near zero-delay adjacent cell interconnection structure an average optimal speedup of 1.4x is revealed, and an average relaxed speedup of 1.25x can be realized simultaneously with a 0.95x LUT utilization decrease.

Comments

This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. The definitive version was published in Frederick, Michael T., and Arun K. Somani. "Beyond the arithmetic constraint: depth-optimal mapping of logic chains in LUT-based FPGAs." Proceedings of the 16th international ACM/SIGDA symposium on Field Programmable Gate Arrays (2008): 37-46. DOI: 10.1145/1344671.1344679.

Copyright Owner

Association for Computing Machinery, Inc. (ACM)

Language

en

File Format

application/pdf

Published Version

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Article Location

 
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