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Electrical and Computer Engineering

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2008 IEEE Workshop on Silicon Errors in Logic-System Effects (SELSE 2008)

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Accepted Manuscript

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2008 IEEE Workshop on Silicon Errors in Logic-System Effects (SELSE 2008)

Conference Date

March 26-27, 2008


Austin, TX


Reliability has become a serious concern as systems embrace nanometer technologies. Current reliability enhancement techniques cause slowdown in processor operation. In this work, we propose a novel approach that organizes redundancy in a special way to provide high degree of fault tolerance. Our approach improves performance by reliably adapting the system clock frequency during run time, based on the current running application and environmental conditions. The organization of redundancy in the proposed conjoined processor supports overclocking, provides concurrent error detection and recovery capability for soft errors, timing errors, intermittent faults and detects silicon defects. The fast recovery process requires no checkpointing and takes three cycles. Post-layout timing annotated gate level simulations of a conjoined two stage arithmetic pipeline shows that our approach achieves near 100% fault coverage, and a performance improvement of 21%. A five stage in-order conjoined pipeline processor was designed and implemented to verify correctness of the proposed architecture.


This is a manuscript of the presentation Subramanian, Viswanathan, Naga D. Avirneni, and Arun K. Somani. "Conjoined processor: a fault tolerant high performance microprocessor." 2008 IEEE Workshop on Silicon Errors in Logic-System Effects (SELSE 2008), March 26-27, 2008, Austin, TX. Posted with permission.


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