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Electrical and Computer Engineering

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2009 IEEE Workshop on Silicon Errors in Logic-System Effects (SELSE 2009)

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Accepted Manuscript

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2009 IEEE Workshop on Silicon Errors in Logic-System Effects (SELSE 2009)

Conference Date

March 24-25, 2009


Stanford, CA


In this paper, we address the issue of soft errors in random logic and develop solutions that provide fault tolerance capabilities without logic duplication. First, we present a circuit level soft error mitigation technique which allows systems to operate without the performance overhead of soft error detection and correction circuitry. This is achieved by sampling data using our Soft Error Mitigation (SEM) register cell, which uses a distributed and temporal voting scheme for soft error detection and correction. Next, we present a scheme to concurrently detect and correct soft and timing errors using a Soft and Timing Error Mitigation (STEM) register cell, which offers soft error protection in aggressive designs that allow overclocking. Timing annotated gate level simulations, using 45nm libraries, of a pipelined adder-multiplier circuit and five-stage DLX processor show that both of our techniques achieve near 100% fault coverage. For DLX processor, even under severe fault injection campaigns, SEM achieves an average performance improvement of 26.58% over a temporal Triple Modular Redundancy (TMR) voter based register cell, while STEM outperforms SEM by 27.42%.


This is a manuscript of the presentation Avirneni, Naga Durga Prasad, Viswanathan Subramanian, and Arun K. Somani. "Soft error mitigation schemes for high performance and aggressive designs." 2009 IEEE Workshop on Silicon Errors in Logic-System Effects (SELSE 2009). March 24-25, 2009, Stanford, CA. Posted with permission.


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