Campus Units

Electrical and Computer Engineering

Document Type

Conference Proceeding

Conference

2009 IEEE/IFIP International Conference on Dependable Systems & Networks

Publication Version

Accepted Manuscript

Link to Published Version

https://doi.org/10.1109/DSN.2009.5270340

Publication Date

2009

Journal or Book Title

2009 IEEE/IFIP International Conference on Dependable Systems & Networks

First Page

185

Last Page

194

DOI

10.1109/DSN.2009.5270340

Conference Title

2009 IEEE/IFIP International Conference on Dependable Systems & Networks

Conference Date

June 29 – July 2, 2010

City

Lisbon, Portugal

Abstract

The threat of soft error induced system failure in high performance computing systems has become more prominent, as we adopt ultra-deep submicron process technologies. In this paper, we propose two techniques, namely soft error mitigation (SEM) and soft and timing error mitigation (STEM), for protecting combinational logic blocks from soft errors. Our first technique (SEM), based on distributed and temporal voting of three registers, unloads the soft error detection overhead from the critical path of the systems. Our second technique (STEM) adds timing error detection capability to guarantee reliable execution in aggressively clocked designs that enhance system performance by operating beyond worst-case clock frequency. We also present a specialized low overhead clock generation scheme that ably supports our proposed techniques. Timing annotated gate level simulations, using 45 nm libraries, of a pipelined adder-multiplier and DLX processor show that both our techniques achieve near 100% fault coverage. For DLX processor, even under severe fault injection campaigns, SEM achieves an average performance improvement of 26.58% over a conventional triple modular redundancy voter based soft error mitigation scheme, while STEM outperforms SEM by 27.42%.

Comments

This is a manuscript of a proceeding published as Avirneni, Naga Durga Prasad, Viswanathan Subramanian, and Arun K. Somani. "Low overhead Soft Error Mitigation techniques for high-performance and aggressive systems." In 2009 IEEE/IFIP International Conference on Dependable Systems & Networks (2009): 185-194. DOI: 10.1109/DSN.2009.5270340. Posted with permission.

Rights

© 2009 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

Copyright Owner

IEEE

Language

en

File Format

application/pdf

Published Version

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