Hybrid data/configuration caching for striped FPGAs
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Abstract
Most custom computing machine (CCM) design has centered around field-programmable gate array (FPGA) technology and rapid prototyping applications. FPGAs are reconfigured to map parts of the application. The performance of an FPGA when used as a virtual hardware engine depends on its reconfiguration granularity. We study the striped FPGA and propose a hybrid mechanism to process a large amount of data using a combination of data and configuration caching.
Comments
This is a manuscript of a proceeding published as Deshpande, Deepali, Arun K. Somani, and Akhilesh Tyagi. "Hybrid data/configuration caching for striped FPGAs." In Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (1999): 294-295. DOI: 10.1109/FPGA.1999.803703. Posted with permission.