Campus Units

Electrical and Computer Engineering, Computer Science

Document Type

Conference Proceeding

Conference

Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines

Publication Version

Accepted Manuscript

Link to Published Version

https://doi.org/10.1109/FPGA.1999.803703

Publication Date

1999

Journal or Book Title

Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines

First Page

294

Last Page

295

DOI

10.1109/FPGA.1999.803703

Conference Title

Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines

Conference Date

April 23, 1999

City

Napa Valley, CA

Abstract

Most custom computing machine (CCM) design has centered around field-programmable gate array (FPGA) technology and rapid prototyping applications. FPGAs are reconfigured to map parts of the application. The performance of an FPGA when used as a virtual hardware engine depends on its reconfiguration granularity. We study the striped FPGA and propose a hybrid mechanism to process a large amount of data using a combination of data and configuration caching.

Comments

This is a manuscript of a proceeding published as Deshpande, Deepali, Arun K. Somani, and Akhilesh Tyagi. "Hybrid data/configuration caching for striped FPGAs." In Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (1999): 294-295. DOI: 10.1109/FPGA.1999.803703. Posted with permission.

Rights

© 1999 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

Copyright Owner

IEEE

Language

en

File Format

application/pdf

Published Version

Share

Article Location

 
COinS