Campus Units

Electrical and Computer Engineering

Document Type

Conference Proceeding

Conference

2006 Sixth European Dependable Computing Conference

Publication Version

Accepted Manuscript

Link to Published Version

https://doi.org/10.1109/EDCC.2006.21

Publication Date

2006

Journal or Book Title

2006 Sixth European Dependable Computing Conference

First Page

77

Last Page

86

DOI

10.1109/EDCC.2006.21

Conference Title

2006 Sixth European Dependable Computing Conference

Conference Date

October 18-20, 2006

City

Coimbra, Portugal

Abstract

The importance of fault tolerance at the processor architecture level has been made increasingly important due to rapid advancements in the design and usage of high performance devices and embedded processors. System level solutions to the challenge of fault tolerance flag errors and utilize penalty cycles to recover through the re-execution of instructions. This motivates the need for a hybrid technique providing fault detection as well as fault masking, with minimal penalty cycles for recovery from detected errors. We propose three architectural schemes to protect the control logic of microprocessors against single event upsets (SEUs). High fault coverage with relatively low hardware overhead is obtained by using both fault detection with recovery and fault masking. Control signals are classified as either static or dynamic, and static signals are further classified as opcode dependent and instruction dependent. The strategy for protecting static instruction dependent control signals utilizes a distributed cache of the history of the control bits along with the triple modular redundancy (TMR) concept, while the opcode dependent control signals are protected by a distributed cache which is used to flag errors. Dynamic signals are protected by selective duplication of datapath components. The techniques are implemented on the OpenRISC 1200 processor. Our simulation results show that fault detection with single cycle recovery is provided for 92% of all instruction executions. FPGA synthesis is performed to analyze the associated cycle time and area overheads.

Comments

This is a manuscript of a proceeding published as Ganesh, T. S., Viswanathan Subramanian, and Arun Somani. "SEU Mitigation Techniques for Microprocessor Control Logic." In 2006 Sixth European Dependable Computing Conference (2006): 77-86. DOI: 10.1109/EDCC.2006.21. Posted with permission.

Rights

© 2006 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

Copyright Owner

IEEE

Language

en

File Format

application/pdf

Published Version

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