Campus Units

Electrical and Computer Engineering

Document Type

Conference Proceeding

Conference

37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07)

Publication Version

Accepted Manuscript

Link to Published Version

https://doi.org/10.1109/DSN.2007.90

Publication Date

2007

Journal or Book Title

37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07)

First Page

196

Last Page

205

DOI

10.1109/DSN.2007.90

Conference Title

37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07)

Conference Date

June 25-28, 2007

City

Edinburgh, UK

Abstract

Synchronous circuits are typically clocked considering worst case timing paths so that timing errors are avoided under all circumstances. In the case of a pipelined processor, this has special implications since the operating frequency of the entire pipeline is limited by the slowest stage. Our goal, in this paper, is to achieve higher performance in superscalar processors by dynamically varying the operating frequency during run time past worst case limits. The key objective is to see the effect of overclocking on superscalar processors for various benchmark applications, and analyze the associated overhead, in terms of extra hardware and error recovery penalty, when the clock frequency is adjusted dynamically. We tolerate timing errors occurring at speeds higher than what the circuit is designed to operate at by implementing an efficient error detection and recovery mechanism. We also study the limitations imposed by minimum path constraints on our technique. Experimental results show that an average performance gain up to 57% across all benchmark applications is achievable.

Comments

This is a manuscript of a proceeding published as Subramanian, Viswanathan, Mikel Bezdek, Naga D. Avirneni, and Arun Somani. "Superscalar processor performance enhancement through reliable dynamic clock frequency tuning." In 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07), (2007): 196-205. DOI: 10.1109/DSN.2007.90. Posted with permission.

Rights

© 2007 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

Copyright Owner

IEEE

Language

en

File Format

application/pdf

Published Version

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