Campus Units

Computer Science, Electrical and Computer Engineering

Document Type

Conference Proceeding

Conference

FPGA '99: ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays

Publication Version

Accepted Manuscript

Link to Published Version

https://doi.org/10.1145/296399.296461

Publication Date

1999

Journal or Book Title

Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays

First Page

206

Last Page

214

DOI

10.1145/296399.296461

Conference Title

FPGA '99: ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays

Conference Date

February 1999

City

Monterey, CA

Abstract

Striped FPGA [1], or pipeline-reconfigurable FPGA provides hardware virtualization by supporting fast run-time reconfiguration. In this paper we show that the performance of striped FPGA depends on the reconfiguration pattern, the run time scheduling of configurations through the FPGA. We study two main configuration scheduling approaches: Configuration Caching and Data Caching. We present the quantitative analysis of these scheduling techniques to compute their total execution cycles taking into account the overhead caused by the IO with the external memory. Based on the analysis we can determine which scheduling technique works better for the given application and for the given hardware parameters.

Comments

This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. The definitive version was published in Deshpande, Deepali, Arun K. Somani, and Akhilish Tyagi. "Configuration caching vs data caching for striped FPGAs." In Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, pp. 206-214. 1999. DOI: 10.1145/296399.296461.

Copyright Owner

ACM

Language

en

File Format

application/pdf

Published Version

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Article Location

 
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