Campus Units

Electrical and Computer Engineering

Document Type

Conference Proceeding

Conference

26th International Symposium on Computer Architecture (ISCA '99)

Publication Version

Accepted Manuscript

Link to Published Version

https://doi.org/10.1109/ISCA.1999.765955

Publication Date

1999

Journal or Book Title

Proceedings of the 26th International Symposium on Computer Architecture (ISCA '99)

First Page

246

Last Page

255

DOI

10.1109/ISCA.1999.765955

Conference Title

26th International Symposium on Computer Architecture (ISCA '99)

Conference Date

May 2-4, 1999

City

Atlanta, GA

Abstract

Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it difficult to trade between the level of data integrity and the chip area requirement. We focus on transient fault tolerance in primary cache memories and develop new architectural solutions to maximize fault coverage when the budgeted silicon area is not sufficient for the conventional configuration of an error checking code. The underlying idea is to exploit the corollary of reference locality in the organization and management of the code. A higher protection priority is dynamically assigned to the portions of the cache that are more error-prone and have a higher probability of access. The error-prone likelihood prediction is based on the access frequency. We evaluate the effectiveness of the proposed schemes using a trace-driven simulation combined with software error injection using four different fault manifestation models. From the simulation results, we show that for most benchmarks the proposed architectures are effective and area efficient for increasing the cache integrity under all four models.

Comments

This is a manuscript of a proceeding published as Kim, Seongwoo, and Arun K. Somani. "Area efficient architectures for information integrity in cache memories." In Proceedings of the 26th International Symposium on Computer Architecture, pp. 246-255. IEEE, 1999. DOI: 10.1109/ISCA.1999.765955. Posted with permission.

Rights

© 1999 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

Copyright Owner

IEEE

Language

en

File Format

application/pdf

Published Version

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