Campus Units

Electrical and Computer Engineering

Document Type

Conference Proceeding

Conference

2021 IEEE 32nd International Conference on Application-specific Systems, Architectures and Processors (ASAP)

Publication Version

Accepted Manuscript

Link to Published Version

https://dx.doi.org/10.1109/ASAP52443.2021.00026

Publication Date

2021

Journal or Book Title

2021 IEEE 32nd International Conference on Application-specific Systems, Architectures and Processors (ASAP)

First Page

125

Last Page

132

DOI

10.1109/ASAP52443.2021.00026

Conference Title

2021 IEEE 32nd International Conference on Application-specific Systems, Architectures and Processors (ASAP)

Conference Date

July 7-9, 2021

Abstract

Convolutional Neural Networks (CNNs) have exceeded human accuracy in many Computer Vision tasks, such as Image Classification, Object Detection, Image Segmentation, etc. This advancement is due to the efficient manual design of CNNs in initially, followed by automated design through Neural Architecture Search (NAS). In parallel to neural network design, advances in Accelerator hardware design, such as Google’s Tensor Processing Unit (TPU), Eyeriss, etc., also occurred for efficient processing of CNN forward propagation. The heart of these accelerators is an array processor (Systolic Array) of a fixed dimension, that limits the amount of CNN computation that can be carried out in a single clock cycle. While NAS is able to produce efficient neural architectures, the networks need to be co-designed with respect to the underlying array dimensions to obtain the best performance. In this paper, we introduce "Array Aware Neural Architecture Search" to automatically design efficient CNNs for a fixed array-based neural network accelerator. Previous Hardware Aware NAS methods consider a fixed search space for different hardware platforms and search within its predefined space. We explore the search space based on the underlying hardware array dimensions to design a more efficient CNN architectures for optimal performance. We observe that our proposed NAS methods on the CIFAR-10 dataset produce similar accuracy as the baseline network while saving a substantial number of cycles on the Array.

Comments

This is a manuscript of a proceeding published as Chitty-Venkata, Krishna Teja, and Arun K. Somani. "Array-Aware Neural Architecture Search." In 2021 IEEE 32nd International Conference on Application-Specific Systems, Architectures and Processors (ASAP), pp. 125-132. IEEE, 2021. DOI: 10.1109/ASAP52443.2021.00026. Posted with permission.

Rights

© 2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

Copyright Owner

IEEE

Language

en

File Format

application/pdf

Published Version

Share

 
COinS