Campus Units

Electrical and Computer Engineering

Document Type

Article

Publication Date

12-2015

Journal or Book Title

International Journal of Reconfigurable Computing

Volume

2015

First Page

826283-1

Last Page

826283-12

DOI

10.1155/2015/826283

Abstract

On-chip multiport memory cores are crucial primitives for many modern high-performance reconfigurable architectures and multicore systems. Previous approaches for scaling memory cores come at the cost of operating frequency, communication overhead, and logic resources without increasing the storage capacity of the memory. In this paper, we present two approaches for designing multiport memory cores that are suitable for reconfigurable accelerators with substantial on-chip memory or complex communication. Our design approaches tackle these challenges by banking RAM blocks and utilizing interconnect networks which allows scaling without sacrificing logic resources. With banking, memory congestion is unavoidable and we evaluate our multiport memory cores under different memory access patterns to gain insights about different design trade-offs. We demonstrate our implementation with up to 256 memory ports using a Xilinx Virtex-7 FPGA. Our experimental results report high throughput memories with resource usage that scales with the number of ports.

Comments

This is an article from International Journal of Reconfigurable Computing 2015 (2015): 82683, doi: 10.1155/2015/826283. Posted with permission.

Rights

Copyright © 2015 Kevin R. Townsend et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Copyright Owner

Kevin R. Townsend et al.

Language

en

File Format

application/pdf

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