Campus Units

Electrical and Computer Engineering

Document Type

Article

Publication Version

Published Version

Publication Date

8-22-2016

Journal or Book Title

PeerJ Computer Science

Volume

2

First Page

e79

DOI

10.7717/peerj-cs.79

Abstract

Timing Speculation (TS) is a widely known method for realizing better-than-worst-case systems. Aggressive clocking, realizable by TS, enable systems to operate beyond specified safe frequency limits to effectively exploit the data dependent circuit delay. However, the range of aggressive clocking for performance enhancement under TS is restricted by short paths. In this paper, we show that increasing the lengths of short paths of the circuit increases the effectiveness of TS, leading to performance improvement. Also, we propose an algorithm to efficiently add delay buffers to selected short paths while keeping down the area penalty. We present our algorithm results for ISCAS-85 suite and show that it is possible to increase the circuit contamination delay by up to 30% without affecting the propagation delay. We also explore the possibility of increasing short path delays further by relaxing the constraint on propagation delay and analyze the performance impact.

Comments

This article is published as Avirneni, Naga Durga Prasad, Prem Kumar Ramesh, and Arun K. Somani. "Managing contamination delay to improve Timing Speculation architectures." PeerJ Computer Science 2 (2016): e79. DOI: 10.7717/peerj-cs.79. Posted with permission.

Creative Commons License

Creative Commons Attribution 4.0 License
This work is licensed under a Creative Commons Attribution 4.0 License.

Copyright Owner

The Authors

Language

en

File Format

application/pdf

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