Campus Units
Electrical and Computer Engineering
Document Type
Article
Publication Version
Published Version
Publication Date
2015
Journal or Book Title
IEICE Electronics Express
Volume
12
Issue
20
First Page
20150742
DOI
10.1587/elex.12.20150742
Abstract
An accurate and low-cost technique is proposed for sinusoidal jitter and random jitter estimation in high-speed ADC test. Exploiting the fact that clock jitter is modulated by the slope of input signal, the proposed method can simultaneously extract both information for sinusoidal jitter and random jitter with a single high frequency test. The proposed method is computationally efficient since only one FFT, one IFFT and few simple arithmetic operations are involved. Compared with existing dual-frequency tests and single-frequency tests, both hardware overhead and data acquisition time are saved significantly. Theoretical analysis and simulation results validate the computational efficiency and test accuracy.
Copyright Owner
IEICE
Copyright Date
2015
Language
en
File Format
application/pdf
Recommended Citation
Wu, Minshun; Liu, Zhiqiang; and Chen, Degang J., "Extracting random jitter and sinusoidal jitter in ADC output with a single frequency test" (2015). Electrical and Computer Engineering Publications. 194.
https://lib.dr.iastate.edu/ece_pubs/194
Comments
This article is published as Wu, Minshun, Zhiqiang Liu, and Degang Chen. "Extracting random jitter and sinusoidal jitter in ADC output with a single frequency test." IEICE Electronics Express 12, no. 20 (2015): 20150742. doi: 10.1587/elex.12.20150742. Posted with permission.