Campus Units

Electrical and Computer Engineering

Document Type

Article

Publication Version

Accepted Manuscript

Publication Date

9-2006

Journal or Book Title

IEEE Transactions on Circuits and Systems II: Express Briefs

Volume

53

Issue

9

First Page

946

Last Page

950

DOI

10.1109/TCSII.2006.880336

Abstract

Applications, depending on their nature, demand either higher computing capacity, larger data-storage capacity, or both. Hence, providing on-chip memory and computing resources that are fixed in nature is expensive and does not enable an efficient utilization of on-chip silicon real estate. In this brief, we design the circuit of an adaptive register file computing (ARC) unit, a novel on-chip dual-role circuit with a minimal area overhead of 0.233 mm 2 at 0.18-mu technology. It supplements the conventional register bank to provide larger register storage capacity or acts as a specialized computing unit to provide higher on-chip computing capacity, depending on the requirement of a specific application. The brief discusses the circuit-level details for the implementation of the dual-role ARC unit, its integration in a wide-issue processor pipeline, and the corresponding performance enhancement in various multimedia applications.

Comments

This is a manuscript of an article published as Sangireddy, Rama, and Arun K. Somani. "On-chip adaptive circuits for fast media processing." IEEE Transactions on Circuits and Systems II: Express Briefs 53, no. 9 (2006): 946-950. DOI: 10.1109/TCSII.2006.880336. Posted with permission.

Rights

© 2006 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

Copyright Owner

IEEE

Language

en

File Format

application/pdf

Published Version

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