Degree Type


Date of Award


Degree Name

Master of Science


Electrical and Computer Engineering

First Advisor

Randall L. Geiger


The rapid shrinking of feature sizes in CMOS processes has enabled high density integration of multi-core systems. However, the corresponding increase in component and local power densities induces thermal stress that can severely affect the reliability of the integrated circuits. To improve the power and thermal management for multi-core systems, an array of temperature sensors is now used to locally monitor the die temperature and provide feedback to the controller for efficient load management and/or load balancing. These temperature sensors must be very small (minimum area overhead) and low power, must have low supply sensitivity, and must provide accurate temperature measurements over a limited operating range.

This thesis provides fundamental analysis of a CMOS Widlar reference generator and the synthesis of a P-Type reverse Widlar temperature sensor. This is followed by the introduction of a 4-transistor multiple threshold voltage (multi-VT) based temperature sensor. Power supply sensitivity analysis and noise analysis are provided for both the 5-transistors reverse Widlar structure and the 4-transistors multi-VT structure. A full design example of a cascoded multi-VT temperature sensor based upon the low-voltage 4-transistor temperature sensor core is also presented. The cascoded structure includes self-bias generators for biasing of the cascode transistors.

The proposed cascode multi-VT temperature sensor based upon the 4-transistor temperature sensor core is implemented in a digital 65nm process with a 1.2V supply voltage. The circuit expresses the threshold voltage directly at the output, does not require a start-up circuit, and provides temperature measurement over an extended operating range. In this thesis, focus is on how the sensor performs over the -20yC to 100yC temperature range. This sensor can achieve high temperature linearity over this operating range.

In a design example of the cascoded 4-transistor multi-VT sensor implemented in a 65nm process, simulation results were obtained that show a maximum nonlinearity over all process corners of 0.546yC over a 120yC operating range. The supply sensitivity is small with a total variation of 0.44yC due to a y10% variation in the supply voltage. The combined temperature nonlinearity and temperature error due to supply variations is less than 1yC.

A detailed discussion of the operation of the cascode self-biasing circuits relating to stability, start-up circuits, and equilibrium points is presented. By adapting the contraction mapping principle to the multi-loop self-biased multi-VT temperature sensor, it is shown that the proposed circuit has a single stable equilibrium point and thus does not require a startup circuit.


Copyright Owner

Sheng Huang Lee



Date Available


File Format


File Size

150 pages

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