Degree Type
Dissertation
Date of Award
2008
Degree Name
Doctor of Philosophy
Department
Electrical and Computer Engineering
First Advisor
Zhao Zhang
Abstract
With increasing speed and power density, high-performance memories, including fully buffered DIMM and DDR2 DRAM, now begin to require dynamic thermal management (DTM) as processors and hard drives did. The DTM of memories, nevertheless, is different in that it should take the processor performance and power consumption into consideration. Existing schemes have ignored that.
We investigate a new approach that controls the memory thermal issues from the source generating memory activities -- the processor. It coordinates processor execution with memory thermal emergency, and therefore improves the overall system performance and power efficiency. For multi-core systems, we propose two schemes called adaptive core gating and coordinated DVFS. The first scheme activates clock gating on selected processor cores, and the second one scales down the frequency and voltage levels of processor cores when the memory is to be overheated. Results from both simulation and real system measurement show that the two schemes can successfully control the memory activities and handle thermal emergency. More importantly, they improve performance significantly under the given thermal envelope.
DOI
https://doi.org/10.31274/etd-180810-2677
Copyright Owner
Jiang Lin
Copyright Date
2008
Language
en
Date Available
2012-04-30
File Format
application/pdf
File Size
93 pages
Recommended Citation
Lin, Jiang, "Thermal modeling and management of DRAM memory systems" (2008). Graduate Theses and Dissertations. 10978.
https://lib.dr.iastate.edu/etd/10978
