Date of Award
Master of Science
Electrical and Computer Engineering
Phillip H. Jones
Integrated circuits have become more complex over the past few years. As processes have improved, it has become possible to pack an ever increasing number of transistors into an Integrated Circuit (IC). At the same time, the functions being performed in the ICs have increased in complexity many fold. The end result is that modern ICs are not only denser, but also have a larger chip area. As a result of both of these factors, maintaining a high yield has become a problem for the IC industry. This problem is present in the manufacturing process for all integrated circuits. This work, however, only focuses on Field Programmable Gate Arrays (FPGA).
FPGAs are a type of programmable hardware that allow arbitrary digital circuits to be implemented into the fabric after the manufacturing process. In this work I propose a method that could allow manufacturers to increase chip yields by allowing FPGAs with some manufacturing errors to be used. Evaluation experiments suggest that this method can tolerate up to 30\% errors in the FPGA's logic fabric without significant reduction in circuit performance as compared to smaller FPGA chips with an equivalent amount of non-faulty logic. This could potentially allow manufacturers to sell larger, faulty chips as a low cost alternative to smaller perfectly manufactured chips.
In brief, the proposed method adds a phase to the tool chain flow that tests and identifies faulty areas in the chip. The information about the faulty areas can then be fed back into the tool flow of the FPGA. This allows the tool chain to avoid the faulty areas of the chip and still place the circuit on the chip in an efficient manner, if possible. The approach aims to reclaim some FPGA ICs that would have ordinarily been classified as unusable and discarded, thus increasing the effective FPGA manufacturing yields.
Gupte, Adwait, "A slice fault aware tool chain for FPGAs" (2011). Graduate Theses and Dissertations. 11996.