Degree Type


Date of Award


Degree Name

Master of Science


Electrical and Computer Engineering

First Advisor

Akhilesh Tyagi


The consistent advances in IC technology result in ever increasing number of transistors. There is more and more interest attracted on the issue of using these transistors in computing more efficiently. The CMP (Chip Multi &ndash processors) is predicted to be one of the most promising solutions for this problem in future. The heterogeneous CMP is supposed to provide more computing efficiency compared to the homogeneous CMP architecture; but it requires complex processing art for manufacturing, which makes it less competitive in the old era. Nowadays, the complicate SOC(System On Chip) manufacturing techniques are pacing fast. This is leading us inexorably to heterogeneous CMP with diverse computing style resources like general purpose CPU, GPU, FPGA, and ASIC cores. In the heterogeneous CMP architecture, the generous purpose CPU provides coverage for all computing, while the non von &ndash Neumann cores harvest energy and processing time for specific computing.

The polymorphic system is defined as a heterogeneous system that enable a computing thread to be dynamically selected and mapped to multiple kinds of cores. A polymorphic thread is compiled for multiple morphisms afforded by these diverse cores. The resulting polymorphic computing systems solve two problems. (1) Polymorphic threads enable more complex, dynamic trade &ndash offs between delay and power consumption. A piecewise cobbling of multiple morphism energy &ndash delay profiles offers a richer Energy &ndash Delay(ED) profile for the entire application. This in turn helps scale the proverbial ITRS &rdquo red &ndash brick power wall &rdquo. (2) The OS scheduler not only picks a thread to run, it also chooses its morphism. Previously, the scientists and engineers prefer using the numerical E · T results to evaluate the design trade &ndash offs, which is challenged to not fit on the future mobile systems design in this thesis. In the mobile systems, whose primary role is &ldquo enhanced terminals &rdquo &ndash user interface to cloud hosted computing backbone, user satisfaction ought to be the primary goal. We propose a scheduler to target User Satisfaction Index (USI) functions. In this thesis, we develop a model for a mobile polymorphic embedded system. This model primarily abstracts the queuing process of the threads in the OS operation. We integrate a polymorphic scheduler in this model to assess the application design space offered by polymorphic computing. We explore several greedy versions of a polymorphic scheduler to improve the user satisfaction driven QoS. We build a polymorphic system simulation platform based on SystemC to validate our theoretical analysis of a polymorphic system. We evaluate our polymorphic scheduler on a variety of application mix with various metrics. We further discuss the feasibility of USI &ndash based polymorphic scheduler by identifying its strengths and weaknesses in relation to the application design space based on the simulation results.


Copyright Owner




File Format


File Size

55 pages