Degree Type

Dissertation

Date of Award

2016

Degree Name

Doctor of Philosophy

Department

Electrical and Computer Engineering

Major

Computer Engineering

First Advisor

Phillip H. Jones

Abstract

The use of hardware-based solutions for accelerating real-time and embedded system appli- cations is limited by the scarceness of hardware resources. By their nature, being limited by the silicon area available, hardware solutions cannot scale in size as easily as their software counter- parts. I assert a hardware-software co-design approach is required to elegantly overcome these limitations. In the first part of this dissertation, I demonstrate the feasibility of this approach by presenting a new hybrid priority queue architecture, which can be managed in hardware and/or software. As an application of this hybrid architecture, I then present a scalable task scheduler for real-time systems that reduces scheduler processing overhead and improves timing determinism of the scheduler. Performance evaluations of our Field Programmable Gate Array (FPGA)-based system-on-chip prototype shows up to a 90% reduction in scheduling overhead and a 98% decrease in scheduler execution time variation, when the scheduler is managed by hardware as compared to software.

As recent trends in real-time and embedded systems show, applications of different criticality are being executed on a single hardware platform driven by the need to reduce size, cost and power requirements. In these mixed criticality systems, it is necessary to ensure the non-critical tasks do not interfere with the timing behavior of safety-critical tasks. In the second part of this dissertation, I investigate hardware architectures that are aware of application criticality and can adapt to changing operating conditions to provided better timing guarantees for critical tasks, while improving overall resource utilization. In support of this approach, I present a criticality aware cache architecture for mixed criticality real-time systems. As a part of the proposed cache design, a new cache replacement policy called Least Critical (LC) is presented, where critical tasks’ data is least likely to be evicted from the cache. Experimental results illustrate the impact of the LC cache replacement policy on the response time of critical tasks, and on overall application performance.

Copyright Owner

Chetan Kumar Nagamangala Govindaiah

Language

en

File Format

application/pdf

File Size

100 pages

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