Title
Degree Type
Dissertation
Date of Award
2016
Degree Name
Doctor of Philosophy
Department
Electrical and Computer Engineering
Major
Computer Engineering (Computing and Networking Systems)
First Advisor
Joseph Zambreno
Abstract
There are hundreds of papers on accelerating sparse matrix vector multiplication (SpMV), however, only a handful target FPGAs. Some claim that FPGAs inherently perform inferiorly to CPUs and GPUs. FPGAs do perform inferiorly for some applications like matrix-matrix multiplication and matrix-vector multiplication. CPUs and GPUs have too much memory bandwidth and too much floating point computation power for FPGAs to compete. However, the low computations to memory operations ratio and irregular memory access of SpMV trips up both CPUs and GPUs. We see this as a leveling of the playing field for FPGAs.
Our implementation focuses on three pillars: matrix traversal, multiply-accumulator design, and matrix compression. First, most SpMV implementations traverse the matrix in row-major order, but we mix column and row traversal. Second, To accommodate the new traversal the multiply accumulator stores many intermediate y values. Third, we compress the matrix to increase the transfer rate of the matrix from RAM to the FPGA. Together these pillars enable our SpMV implementation to perform competitively with CPUs and GPUs.
DOI
https://doi.org/10.31274/etd-180810-4826
Copyright Owner
Kevin Rice Townsend
Copyright Date
2016
Language
en
File Format
application/pdf
File Size
113 pages
Recommended Citation
Townsend, Kevin Rice, "Computing SpMV on FPGAs" (2016). Graduate Theses and Dissertations. 15227.
https://lib.dr.iastate.edu/etd/15227
