Degree Type
Thesis
Date of Award
2017
Degree Name
Master of Science
Department
Electrical and Computer Engineering
Major
Computer Engineering
First Advisor
Arun K. Somani
Abstract
With the ever-decreasing feature sizes, static power dissipation has become a concern in computing devices. On-chip memories are a major contributor towards the processor’s leakage power dissipation due to their large transistor count. We propose a Low Leakage Energy Architecture for Caches, called LowLEAC to minimize the static power dissipation in caches made of CMOS SRAM cells. This technique is based on keeping only k most recently used cache lines powered on other lines powered off to reduce the leakage power dissipation. The control however increases the dynamic power due to re-fetching of data. To overcome that, we deploy CMOS compatible nonvolatile SRAM cell, called cNVSRAM, to implement caches. The cNVSRAM cell works as a conventional SRAM in the regular mode and saves the data in a non-volatile back up when a cache line is turned off or put in the sleep mode. The non-volatile back up mode helps improve the dependability of the cache and avoids the penalty occurred due to loss of data from the inactive cache lines. With a small area penalty, LowLEAC achieves 18% energy savings with insignificant impact on the performance. LowLEAC is a suitable architecture for cache memory in mobile computing devices to minimize battery power consumption and reduce heat.
DOI
https://doi.org/10.31274/etd-180810-4936
Copyright Owner
Rashmi Parisa Girmal
Copyright Date
2017
Language
en
File Format
application/pdf
File Size
43 pages
Recommended Citation
Girmal, Rashmi Parisa, "LowLEAC: Low leakage energy architecture for caches" (2017). Graduate Theses and Dissertations. 15308.
https://lib.dr.iastate.edu/etd/15308