Degree Type

Dissertation

Date of Award

2016

Degree Name

Doctor of Philosophy

Department

Electrical and Computer Engineering

Major

Computer Engineering

First Advisor

Chris Chu

Abstract

As the technology nodes keep shrinking following Moore's law, lithography becomes increasingly critical to the fabrication of integrated circuits. The 193nm ArF immersion lithography (193i) has been a common technique for manufacturing integrated circuits. However, the 193i with single exposure has finally reached its printability limit at the 28nm technology node. To keep the pace of Moore's law, design for manufacturability (DFM) is demonstrated to be effective and cost-efficient. The concept of DFM is to modify the design of integrated circuits in order to make them more manufacturable. Tremendous efforts have been made for DFM in advanced lithography technologies. In general, the progress can be summarized in four directions. (1) Advanced lithography process by novel patterning techniques and next-generation lithography; (2) High performance lithography simulation approach in mask synthesis; (3) Physical design (PD) methodology with lithography manufacturability awareness; (4) Robust design flow integrating emerging PD challenges. Accordingly, we propose our research topics in those directions. (1) Throughput optimization for self-aligned double patterning (SADP) and e-beam lithography based manufacturing of 1D layout; (2) Design of efficient rasterization algorithm for mask patterns in inverse lithography technology (ILT); (3) SADP-aware detailed routing; (4) SADP-aware detailed routing with consideration of double via insertion and via manufacturability; (5) Pin accessibility driven detailed placement refinement.

In our first research work, we investigate throughput optimization of 1D layout manufacturing. SADP is a mature lithography technique to print 1D gridded layout for advanced technologies. However, in 16nm technology node, trim mask pattern in SADP lithography process may not be printable using 193i along within a single exposure. A viable solution is to complement SADP with e-beam lithography. To order to increase the throughput of 1D layout manufacturing, we consider the problem of e-beam shot minimization subject to bounded line-end extension constraints. Two different approaches of utilizing the trim mask and e-beam to print a 1D layout are considered. The first approach is trimming by end cutting, in which trim mask and e-beam are used to chop up parallel lines at required locations by small fixed rectangles. The second approach is trimming by gap removal, in which trim mask and e-beam are used to rid of all unnecessary portions. We propose elegant integer linear program formulations for both approaches. Experimental results show that both integer linear program formulations can be solved efficiently and have a major speedup compared with previous related work. Furthermore, the pros and cons of the two approaches for manufacturing 1D layout are discussed.

In our second research work, we focus on a critical problem of lithography simulation in the design of ILT mask. To reduce the complexity of modern lithography simulation, a widely used approach is to first rasterize the ILT mask before it is inputted to the simulation tool. Accordingly, we propose a high performance rasterization algorithm. The algorithm is based on a pre-computed look-up table. Every pixel in the rasterized image is firstly identified its category: exception or non-exception. Then convolution for every pixel can be performed by a single or multiple look-up table queries depending on its category. In addition, the proposed algorithm has shift invariant property and can be applied for all-angle mask patterns in ILT. Experimental results demonstrate that our approach can speedup conventional rasterization process by almost 500x while maintaining small variations in critical dimension.

In our third research work, we concentrate on SADP-aware detailed routing. SADP is a promising manufacturing option for sub-22nm technology nodes due to its good overlay control. To ensure layout is manufacturable by SADP, it is necessary to consider it during layout configuration, e.g., detailed routing stage. However, SADP process is not intuitive in terms of mask design, and considering it during detailed routing stage is even more challenging. We investigate both of two popular types of SADP: spacer-is-dielectric and spacer-is-metal. Different from previous works, we apply the color pre-assignment idea and propose an elegant graph model which captures both routing and SADP manufacturing cost. They greatly simplify the problem to maintain SADP design rules during detailed routing. A negotiated congestion based rip-up and reroute scheme is applied to achieve good routability while maintaining SADP design rules. Our approach can be extended to consider other multiple patterning lithography during detailed routing, e.g., self-aligned quadruple patterning targeted at sub-10nm technology nodes. Compared with state-of-the-art academic SADP-aware detailed routers, we offer routing solution with better quality of result.

In our fourth research work, we extend our SADP-aware detailed routing to consider other manufacturing issues. Both SADP and triple patterning lithography (TPL) are potential layout manufacturing techniques in 10nm technology node. While metal layers can be printed by SADP, via layer manufacturing requires TPL. Previous works on SADP-aware detailed routing do not automatically guarantee via layer are manufacturable by TPL. We extend our SADP-aware detailed routing to consider TPL manufacturability of via layer. Double via insertion is an effective method to improve yield and reliability in integrated circuits manufacturing. We also consider it in our SADP-aware detailed routing to further improve insertion rate. A problem of TPL-aware double via insertion in the post routing stage is proposed. It is solved by both integer linear programming and high-performance heuristic. Experimental results demonstrate that our SADP-aware detailed routing can ensure via layer are TPL manufacturable and improve double via insertion rate.

In our last research work, we target at the enhancement of pin access. The significant increased number of routing design rules in advanced technologies has made pin access an emerging difficultly in detailed routing. Resolving pin access in detailed routing may be too late due to the fix pin locations. Thus, we consider pin access in earlier design stage, i.e., detailed placement stage, when perturbation of cell placement is allowed. A cost function is proposed to model pin access for each pin-to-pin connection in detailed routing. A two-phase detailed placement refinement is performed to improve pin access, and refinement techniques are limited to cell flipping, same-row adjacent cell swap and cell shifting. The problem is solved by dynamic programming and linear programming. Experimental results demonstrate that the proposed detailed placement refinement improve pin access and reduce the number of unroutable nets in detailed routing significantly.

DOI

https://doi.org/10.31274/etd-180810-5528

Copyright Owner

Yixiao Ding

Language

en

File Format

application/pdf

File Size

153 pages

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