Degree Type

Thesis

Date of Award

2017

Degree Name

Master of Science

Department

Electrical and Computer Engineering

Major

Electrical Engineering

First Advisor

Randall L. Geiger

Abstract

Dynamic comparators are popular structures used in analog circuits such as RFID tags, ADC, memory modules, etc. Compared with traditional open-loop amplifiers that can be used as a comparator, well-designed dynamic comparators are usually faster and more power-efficient, but dynamic CMPs also have some problems. Device mismatch-induced offset voltages is a major challenge when designing dynamic comparators because device mismatch is a random variable that is non-predictable during the design stage. There are many popular dynamic CMP structures; one of them is the Lewis-Gray dynamic comparator [1]. Many authors have introduced alternative dynamic comparator structures which they claim are less affected by device mismatch than the Lewis-Gray circuit but few present a comprehensive and reasonable comparison method. In those papers, different modifications are implemented in order to minimize device mismatch offset, one popular way is to add an amplifier stage before the dynamic comparator. The input signals are amplified in the first amplifier stage before going into the second dynamic comparator stage. Since the outputs of the first stage have a larger difference comparing with the inputs, the offset requirement for the dynamic comparator is loosened. However, the offset still has room for improvement.

In this work, a low offset dynamic comparator with morphing amplifier is proposed. It doesn’t have two independent stages. Instead, the amp is inherently integrated into a dynamic comparator, and it yields better offset performance. Moreover, a new fair and comprehensive offset comparison method is also introduced.

Copyright Owner

Xilu Wang

Language

en

File Format

application/pdf

File Size

70 pages

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