Date of Award
Master of Science
Electrical and Computer Engineering
Biometric authentication is becoming an increasingly prevalent way to identify a person based on unique physical traits such as the fingerprint, the face, and/or the iris. The iris stands out particularly among these traits due to its relative invariability with time and high uniqueness. However, iris recognition without special, dedicated tools like near-infrared (NIR) cameras and stationary high-performance computers is a challenge. Solutions have been proposed to target mobile platforms like smart phones and tablets by making use of the RGB camera commonly found on those platforms. These solutions tend to be slower than the former due to the decreased performance achieved in mobile processors. This work details an approach to solve the mobility and performance problems of iris segmentation in current solutions by targeting an FPGA-based SoC. The SoC allows us to run the iris recognition system in software, while accelerating slower parts of the system by using parallel, dedicated hardware modules. The results show a speedup in segmentation 2X when compared to an x86-64 platform and 46X when compared to an ARMv7 platform.
Avey, Joseph, "An FPGA-based hardware accelerator for iris segmentation" (2018). Graduate Theses and Dissertations. 16310.