Degree Type


Date of Award


Degree Name

Master of Science


Electrical and Computer Engineering


Computer Engineering

First Advisor

Joseph Zambreno


Dynamic Partial Reconfiguration (DPR) can be a useful tool for maximizing FPGA performance while minimizing power consumption and FPGA size requirements. This work explores the application of the DPR technique in a computer vision application that implements two different edge detection algorithms (FASTX and Sobel). This technique could allow for a similar computer vision system to be realized on a smaller, low-power chipset. Different algorithms can have unique characteristics that yield better performance in certain scenarios; the best algorithm for the current scenario may change during runtime. However, implementing all available algorithms in hardware increases the space and power requirements of the FPGA. We analyze a system that can load an individual edge detection algorithm into the computer vision processing pipeline with negligible interruptions to data processing by using DPR. This application targets the Xilinx UltraScale+ ZCU106 and is able to maintain the same functionality while using an average of 4% less energy when compared to the non-DPR implementation. Additionally, the FPGA utilization for this application is 15% less than that of the traditional implementation that includes both algorithms on the chip at once. These results demonstrate that this technique could allow a similar computer vision system to be realized on a smaller, low-power chipset.

Copyright Owner

Robert Cole Wernsman



File Format


File Size

38 pages