The increasing complexity of the System-on-Chips (SoCs) used in mission-critical systems such as autonomous cars or planes has led to the need for and various developments of online testing and monitoring methods to monitor circuit functionality and performance of these SoCs. However, the insertion of these monitoring circuits, especially when they are non-ideal, can negatively impact the normal operation or even basic function of the original circuits. For example, glitches generated by clocks or switches in the monitoring circuits can be coupled into the nodes under test (NUTs) through parasitic capacitors in the original circuits.

To reduce the negative impact on the normal operation, the widely accepted method is inserting analog buffers between the NUTs and the monitoring circuits. For example, a well-designed analog buffer can dramatically reduce the glitch magnitudes coupled to the NUTs by as much as 95%. This thesis will start with systematical analysis on six widely used analog buffers, namely, two Super Source Followers (SSF), two Flipped Voltage Followers (FVF), and 5-Transistor and 7-Transistor buffers. Following that, strategies of optimizing reverse isolation (reverse gain) of these buffers will be derived to enable further reductions of the negative impact of the monitoring circuits. Furthermore, the buffers will be designed and simulated with GF130nm process, and the performance results, such as gain, linearity, reverse gain, etc. will be summarized in a comparison table for easy access. Finally, recommendations of buffers to be used for different applications will be provided.