Degree Type

Dissertation

Date of Award

2020

Degree Name

Doctor of Philosophy

Department

Electrical and Computer Engineering

Major

Electrical Engineering (Very Large Scale Integration)

First Advisor

Degang Chen

Abstract

Integrated Circuits (ICs) are used in a myriad of applications and impact our lives every single day. Some of these applications are mission critical, like automotive, medical equipment, aircrafts etc., and thus have stringent quality and reliability requirements. Extensive testing is needed to guarantee adherence to these requirements. Test time and cost are typically very high for Analog and mixed-signal circuits. Analog-to-Digital Converters (ADCs) and Digital-to-Analog-Converters (DACs) are critical components of many of these ICs, and the cost associated with their testing often dominates the overall test cost of the ICs. There is thus an urgent need to develop methods that reduce test time and cost of data converters, and also ensure their reliability post deployment.

In this dissertation, we will provide several solutions to address these issues, with a focus on DACs. First, a segmented linearity testing method called uSMILE will be presented for reducing test time and thus cost of DAC linearity test by reducing the number of measurements required to estimate the nonlinearity of the DAC. Next, the uSMILE-ROME algorithm for DAC testing will be described. This not only reduces test time but significantly reduces test cost by eliminating the need for high precision measurement devices for linearity testing of high resolution DACs. A cheap on-board/on-chip digitizer with comparable resolution and worse linearity than the DAC under test can be used to get an accurate estimation of the DAC INL. The algorithm will further be adapted so that it can be run on-chip, enabling Built-in Self-test and Self-calibration of DACs, which ensures their long-term reliability. The uSMILE algorithm will then be modified to estimate and calibrate dynamic errors in the DAC, in addition to static errors. This enables low-cost high purity sine wave generation using a non-linear DAC. Finally, a Concurrent Sampling (CS) method will be introduced for measuring a multitude of analog DC voltages on-chip concurrently using local comparators and a calibrated DAC. The previously mentioned test and calibration schemes can be used for DAC calibration.

uSMILE and its variants are currently used for production testing of multiple products at Texas Instruments and other semiconductor companies to reduce DAC linearity test time. A uSMILE-ROME based DAC built-in self-test and self-calibration scheme is being developed on a chip at NXP semiconductors. These BIST techniques, combined with Concurrent Sampling, enable real-time measurement of analog voltages, and will have a significant impact on the semiconductor industry because it addresses a growing need for automotive test and reliability.

DOI

https://doi.org/10.31274/etd-20200902-21

Copyright Owner

Shravan Kumar Chaganti

Language

en

File Format

application/pdf

File Size

197 pages

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