System-on-chips (SoCs) with analog and mixed-signal (AMS) blocks are used everywhere in real-life applications, e.g., smart sensors, medical monitoring devices, automotive components, etc. Such applications typically require some sort of power management, sensor interface, signal conditioning, and processing. While modern deep sub-micron technologies benefit digital subsystems with low cost and high data rates, the performance of analog subsystems becomes more difficult to manage because of factors such as lower channel resistance, poorer matching, inferior linearity, and smaller operating voltage ranges. In the coming Internet of Things (IoT) era with more embedded analog functions, the design of the analog portion of a system becomes a bottleneck with respect to performance, time to market and costs.

This dissertation introduces several design techniques for helping recover analog performance for common AMS blocks in SoCs. The main bottleneck of most signal processing SoCs is analog signal processing whose accuracy relies mostly on the matching property of a device array configured into a ratio matrix for signal processing. A general methodology for characterizing device array mismatch, both systematic gradient and random mismatch, is introduced. It can provide information for process engineers to use in optimizing fabrication processes and for circuit designers to use in applying error reduction techniques for achieving acceptable yield. To address gradient errors induced nonlinearity, a practical layout structure and an interpolation method are proposed for string digital-to-analog converter (DAC). It divides a string into multiple smaller substrings and places them in a pattern where both linear and 2nd order gradients are suppressed, with averaging and interpolation implemented at the substrings’ outputs to recover bits of resolution without sacrificing linearity improvement. The proposed structure is validated by both simulation and measurement results. An 8-bit DAC prototype was designed in GlobalFoundries 130nm process and achieves 16-bit linearity performance without trimming and calibration.

Good clocks are also important for mixed-signal systems, because without uniform sampling all standard signal processing theory can fall apart. While smaller geometry size and less parasitic can lead to increased clock speed, with process variations, clocks can suffer from unpredictable duty cycle distortions during generation and distribution. To address this issue, a low-cost and area-efficient analog duty cycle corrector with feedback is proposed.

Good linearity and clean clocks contribute to the relative accuracy of a system, and to achieve high absolute accuracy, a precise and constant reference is needed. A general approach based on natural base expansion is proposed for canceling the VBE curvature of a bipolar transistor and creating sub-ppm/°C voltage references. A prototype realized with both on-chip devices and off-chip components was designed, fabricated, and measured with results demonstrating the first voltage reference with sub-ppm/°C, or 0.8 ppm/°C to be exact, temperature coefficient over a temperature range of 0 °C to 80 °C after optimal trimming.

Good power supplies are also essential for high precision systems, and output-capacitorless low-dropout regulators (OCL-LDOs) have been widely used in SoCs for the purpose of generating clean supplies and providing isolation from noisy blocks. Stability is a basic requirement and achieving satisfactory performance in terms of accuracy, transient response, and power-supply rejection (PSR) is usually a more difficult task. To achieve fast transient response with reasonable current, a dual loop OCL-LDO structure utilizing a super source follower and a flipped voltage follower is proposed. A prototype that can deliver a 20 mA current with only 0.01 mm2 active area was implemented in the UMC 65nm process. While the overall structure is simple and straightforward, it achieves a FOM comparable to the state-of-the-art.