Location

La Jolla, CA

Start Date

1-1-1987 12:00 AM

Description

The final manufacturing process for silicon wafers includes a chemomechanical polishing step. This process gives the silicon wafer its mirror finish, but potentially leaves a thin layer of structurally damaged silicon at the wafer surface. There is at present some concern in the integrated circuit industry that circuit yield and performance in shallow junction, highly integrated MOS IC devices, often with gate oxide thickness in the 100 to 250 Angstrom range, are harmed by such residual damage on incoming wafers. Rather than being completely eliminated by the anneal cycles of the subsequent processing, regions of structural damage on the surface (i. e., polishing damage, scratches, saw marks) have been reported to function as local nucleating sites for stacking faults during oxidation [1]. Similarly, localized surface flaws in the form of minute pits in the silicon surface are found to provide preferential sites for defect generation during dopant diffusion [2]. Also, recent studies by Kugimiya and coworkers have shown that some types of surface defects such as polishing marks, dimples, etc., survive various IC fabrication processes and result in reduced yield [3].

Book Title

Review of Progress in Quantitative Nondestructive Evaluation

Volume

6B

Chapter

Chapter 7: Electronic Materials and Devices

Section

Electronic Materials and Devices

Pages

1353-1360

DOI

10.1007/978-1-4613-1893-4_153

Language

en

File Format

application/pdf

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Jan 1st, 12:00 AM

Nondestructive Characterization of Polishing Damage in Silicon Wafers Using Modulated Reflectance Mapping

La Jolla, CA

The final manufacturing process for silicon wafers includes a chemomechanical polishing step. This process gives the silicon wafer its mirror finish, but potentially leaves a thin layer of structurally damaged silicon at the wafer surface. There is at present some concern in the integrated circuit industry that circuit yield and performance in shallow junction, highly integrated MOS IC devices, often with gate oxide thickness in the 100 to 250 Angstrom range, are harmed by such residual damage on incoming wafers. Rather than being completely eliminated by the anneal cycles of the subsequent processing, regions of structural damage on the surface (i. e., polishing damage, scratches, saw marks) have been reported to function as local nucleating sites for stacking faults during oxidation [1]. Similarly, localized surface flaws in the form of minute pits in the silicon surface are found to provide preferential sites for defect generation during dopant diffusion [2]. Also, recent studies by Kugimiya and coworkers have shown that some types of surface defects such as polishing marks, dimples, etc., survive various IC fabrication processes and result in reduced yield [3].