Degree Type

Dissertation

Date of Award

1991

Degree Name

Doctor of Philosophy

Department

Electrical and Computer Engineering

First Advisor

Arthur V. Pohm

Abstract

This research investigates several problems associated with current multiprocessor interconnection networks, focusing primarily on general-purpose, shared-memory configurations. The project deals with all aspects of the interconnection, from the architectural level to the physical backplane. A multiple-bus based architecture is presented as an alternative to the limitations of current schemes. This dissertation will focus on the logical layer specification;The ActiveBus--a multiple, active bus--interconnection is proposed. Multiple buses increase the bandwidth as well as reliability of the interconnection while the active backplane shows a reduced and uniform capacitive load;A logical layer protocol was designed for each bus to work independently, to achieve fault tolerance. Each bus uses a word-serial approach to keep the total number of bus signal lines manageable. A dual clocking scheme is proposed. The faster clock is used for data transfer. The other clock, refered to as sync clock, is used for arbitration and handshaking;Absence of discontinuities on the bus coupled with a source-synchronous transfer protocol allows data to be streamed at a high rate, thus increasing the pin-efficiency of the bus. The data transmission rate is limited only by clock skew. In addition, the ActiveBus interface unit and the source synchronous protocol move the synchronization penalty from the shared bus to the private buffer in the unit;The protocol uses a new arbitration scheme, termed Previous Priority First. This hybrid control acquisition scheme combines collision detection and priority arbitration to minimize bus access time without requiring additional signal lines. Collision detection provides a quick access in an unsaturated system while priority arbitration guarantees the deterministic election of the master in a saturated system. The scheme also incorporates a fairness mode to minimize starvation and bus access delay in the system;The cache coherence scheme supports both copy-back and write-through policies to reduce the overhead. MOESI protocol with snoopy caches, being the most general, is followed. Message passing and synchronization primitives are provided within the bus protocol to support multiple processor systems. These primitives attempt to minimize the traffic generated by the spin locks or the memory hot spots.

DOI

https://doi.org/10.31274/rtd-180813-9501

Publisher

Digital Repository @ Iowa State University, http://lib.dr.iastate.edu/

Copyright Owner

Sagar Waman Kenkare

Language

en

Proquest ID

AAI9202366

File Format

application/pdf

File Size

229 pages

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