Degree Type
Dissertation
Date of Award
2004
Degree Name
Doctor of Philosophy
Department
Electrical and Computer Engineering
First Advisor
Chris Chu
Abstract
Congestion is one of the main optimization objectives in global routing. However, the optimization performance is constrained because the cells are already fixed at this stage. Therefore, designer can save substantial time and resources by detecting and reducing congested regions during the planning stages. An efficient and yet accurate congestion estimation model is crucial to be included in the inner loop of floorplanning and placement design. In this dissertation, we mainly focus on routing congestion modeling and reduction during floorplanning and placement.
DOI
https://doi.org/10.31274/rtd-180813-9922
Publisher
Digital Repository @ Iowa State University, http://lib.dr.iastate.edu
Copyright Owner
Zion Cien Shen
Copyright Date
2004
Language
en
Proquest ID
AAI3145682
File Format
application/pdf
File Size
132 pages
Recommended Citation
Shen, Zion Cien, "Routing congestion analysis and reduction in deep sub-micron VLSI design " (2004). Retrospective Theses and Dissertations. 1122.
https://lib.dr.iastate.edu/rtd/1122
