Degree Type

Thesis

Date of Award

2008

Degree Name

Master of Science

Department

Electrical and Computer Engineering

First Advisor

Randall Geiger

Second Advisor

Zhengdao Wang

Third Advisor

Degang Chen

Abstract

Track and hold circuits play a key role in mixed-signal, analog to digital interfaces. They are often used as part of the analog to digital conversion (ADC) process whereby a time-varying analog signal is sampled at the transition of a clock signal and subsequently held for a part of the conversion process. This approach is used, in part, because the remainder of the ADC conversion process is adversely affected if the input signal varies during the conversion.;Noise, and in particular thermal noise, is recognized as a major bottleneck limiting the performance of switched-capacitor circuits and it is essential that all of the major contributors to noise are appropriately considered when designing any switched-capacitor circuit. Invariably, switched-capacitor (SC) circuit designers only discuss noise generated in the track mode when reporting noise performance and correspondingly ignore noise generated in the hold mode. In particular, most authors simply use the well-known expression kT/C to represent the variance of sampled thermal noise present on a sampling capacitor [16]-[19]. The spectrum of the continuous-time sample and hold noise has been discussed as the switches capacitor circuitry field evolved [1]-[3] but the early authors didn't discuss the relationship between the spectrum of the sample and hold noise and the sampled noise characterized with the kT/C expression. More important, noise present during the hold mode which affects subsequent sampling has not been discussed in the literature. In the thesis, the continuous noise which is generated during the second phase of a SC circuit will be compared to the S/H noise.;In chapter two of this thesis, a numerical comparison between the RMS value of the continuous-time S/H noise and the sampled kT/C noise is presented. In chapter three, thermal noise present during the hold mode for two switched-capacitor circuits which are often used in analog to digital converters are investigated and compared with the standard sampled noise expression. In chapter four, it is shown that when these switched-capacitor circuits are used in an analog to digital converter with low speed and small resolution, the continuous-time hold noise can be justifiably neglected but when the sample frequency and resolution get higher, the noise that is generated in the hold phase is not negligible and can cause significant performance degradation of the system.

DOI

https://doi.org/10.31274/rtd-180813-16706

Publisher

Digital Repository @ Iowa State University, http://lib.dr.iastate.edu/

Copyright Owner

Yingkun Gai

Language

en

Proquest ID

AAI1460094

OCLC Number

313395396

ISBN

9780549923954

File Format

application/pdf

File Size

73 pages

Share

COinS