Degree Type

Dissertation

Date of Award

2004

Degree Name

Doctor of Philosophy

Department

Electrical and Computer Engineering

First Advisor

Robert J. Weber

Abstract

Wireless communication and its application have been growing rapidly in recent years. With the recent advances in CMOS technology, Radio Frequency CMOS IC design provides a potential solution for System-On-Chip. This dissertation explores the design of a fully integrated CMOS Low-Noise Amplifier for an IEEE 802.11a wireless communication receiver. A new design methodology is presented for optimization of feedback to achieve simultaneous noise and gain match. Two-port noise theory is extended to multi-port noise analysis for a three-port-to-two-port noise transformation. This approach is applied in the design of a 5.3-GHz LNA in a CMOS 0.18-um technology. The measurement gives a nominal forward gain of 5.2 dB, input and output impedance matching of -9.3 dB and -8.9 dB respectively, isolation of -42.8 dB, estimated noise figure of 4.8 dB with the circuit drawing 4.2-mA from a 1.5-V supply. A novel process-variation insensitive network is proposed to realize the on-chip impedance matching that minimizes the effect of process variation. The proposed network utilizes precision matching capacitors to achieve a low sensitivity to process variation. Its performance is demonstrated by Monte Carlo simulations.

DOI

https://doi.org/10.31274/rtd-180813-15349

Publisher

Digital Repository @ Iowa State University, http://lib.dr.iastate.edu/

Copyright Owner

Feng Chen

Language

en

Proquest ID

AAI3190716

File Format

application/pdf

File Size

103 pages

Share

COinS