Degree Type

Thesis

Date of Award

1-1-2001

Degree Name

Master of Science

Department

Electrical and Computer Engineering

Major

Electrical Engineering

Abstract

With the continuous scaling down of very large scale integrated (VLSI) technologies and increased die size, the transistors are much smaller, and hence much faster. On the other hand, interconnects are narrower. So they are more resistive and slower in transmitting signals. This trend has led the interconnect delay to become a significant factor in determining the performance of VLSI designs. As the die size becomes larger, global interconnect length becomes longer. Thus, global interconnect delay is beginning to dominate a larger portion of the overall system performance. In order to take the impact of interconnect delay into account, it is very important to have computationally inexpensive and accurate interconnect delay models. The primary contribution of this thesis is to present two new interconnect delay models, called the Fitted Elmore Delay (FED) and the Improved Effective Capacitance Metric (IECM). The FED model is a simple, efficient and reasonably accurate interconnect performance estimation model. This model uses a curve fitting technique to approximate the accurate Hspice delay data. The functional form used in the curve fitting is derived based on the Elmore Delay (ED) model. Thus, our model has all the advantages of the Elmore Delay model. It has a closed form expression as simple as the ED model and is extremely efficient to compute. More importantly, it is significantly more accurate than the ED model. In fact, because of its striking similarity to the ED model, optimization of the delay with respect to the design parameters can be easily done. When applied to interconnect optimization techniques (i.e., wire sizing), the FED model is three to four times more accurate than the Elmore Delay model. On the other hand, like the ED model, the FED has the limitation of ignoring the resistive shielding problem. This problem occurs when the gate no longer sees the total net capacitance due to the high interconnect resistance. The Improved Effective Capacitance Metric (IECM) overcomes the resistive shielding problem. We adopt the methodology of computing the first three Taylor series coefficients of the driving-point admittance in the circuit. The IECM uses these Taylor coefficients to derive a closed form solution for the effective capacitance that captures the resistive shielding characteristics. The IECM can be implemented with similar simplicity as the Elmore Delay model. We have tested the IECM on a single-load circuit and multiple tree topologies. Experiments show that our model is significantly more accurate than other existing interconnect delay models in capturing the resistive shielding characteristics.

DOI

https://doi.org/10.31274/rtd-20201118-0

Copyright Owner

Arif Ishaq Abou-Seido

Language

en

OCLC Number

47039789

File Format

application/pdf

File Size

58 pages

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