Degree Type

Dissertation

Date of Award

1985

Degree Name

Doctor of Philosophy

Department

Electrical and Computer Engineering

Abstract

The growing complexity of integrated circuits has made simulation, through software-based simulators, very time consuming. The declining cost of hardware and a massive amount of computing time required to simulate logic networks have made the use of hardware simulators very attractive;This dissertation describes the architecture of a specialized, highly parallel, and programmable hardware accelerator for logic simulation. It is designed with commercially available chips in a microprogrammed environment. Any future changes can be accommodated by a change in microcode. High speed is achieved by exploiting parallelism, both in the logic network and the hardware of the processing unit. A standard bus is used for communication between the processing unit and the host computer. A "thick", nonstandard bus is used for communication of data within the processing unit at a very high speed. By using two buses, intermediate simulation results could be sent to the host computer in parallel with the simulation of devices. Devices are simulated in a pipelined fashion. Reliability is increased by providing error detection and correction capability for memories and buses, and by providing built-in hardware for diagnostics in a computer-aided environment. Evaluation programs of new devices can be loaded in the processing unit through the host computer. Event driven simulation with arbitrary delays and signal values have been used. Devices are divided into various categories to utilize system resources efficiently. Any device, simple or functional, can be simulated.

DOI

https://doi.org/10.31274/rtd-180813-5210

Publisher

Digital Repository @ Iowa State University, http://lib.dr.iastate.edu/

Copyright Owner

Vineet Kumar

Language

en

Proquest ID

AAI8514417

File Format

application/pdf

File Size

197 pages

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