Degree Type

Dissertation

Date of Award

1988

Degree Name

Doctor of Philosophy

Department

Electrical and Computer Engineering

First Advisor

Arthur V. Pohm

Abstract

Scan conversion processing is the bottleneck in the image generation process. To solve the problem of smooth shading and hidden surface elimination, a new processor architecture has been invented which has been labeled as a scan conversion processor architecture (SCP). The SCP is designed to perform hidden surface elimination and scan conversion for 64 pixels. The color intensities are dual-buffered so that when one buffer is being updated the other can be scanned out. Z-depth is used to perform the hidden surface elimination. The key operation performed by the SCP is the evaluation of linear functions of a form like F(X,Y) = A * X + B * Y + C. The computation is further simplified by using incremental addition. The z-depth buffer and the color buffers are incorporated onto the same chip. The SCP receives from its preprocessor the information for the definition of polygons and the computation of z-depth and RGB color intensities;Many copies of this processor will be used in a high performance graphics system. The SCP processes one polygon at a time. Many polygons can be processed at the same time when several Bounds-Checking Processors are added to the system. Each Bounds-Checking Processor handles a specific area of the display screen. If one polygon has intersection with a Bounds-Checking Processor's controlled area, the related information will be rebroadcasted to SCPs in that area. The SCP chip uses about 26,000 transistors. 16 SCPs can be put on one chip if the 1 [mu]m CMOS technology is used.

DOI

https://doi.org/10.31274/rtd-180813-11292

Publisher

Digital Repository @ Iowa State University, http://lib.dr.iastate.edu/

Copyright Owner

Han-Uei Huang

Language

en

Proquest ID

AAI8909151

File Format

application/pdf

File Size

65 pages

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