Degree Type
Thesis
Date of Award
2006
Degree Name
Master of Science
Department
Electrical and Computer Engineering
First Advisor
Randall L. Geiger
Abstract
The adaptive bandwidth technique is commonly used to implement fast switching in low-spurious frequency synthesizers. In this technique the high loop bandwidth used during the switching mode has to be restored once switching is complete. The process of restoring the bandwidth adds to the total switching time because of the glitches on the VCO control voltage arising from the perturbation caused in the loop. Often in applications demanding ultra fast switching times and tight error tolerances, the additional settling time due to these secondary glitches can be a significant fraction of the total switching time. In this thesis, a more efficient multi-step bandwidth-switching scheme is proposed that can significantly reduce the total switching time by minimizing the effect of secondary glitches. After satisfactory behavioral simulations, a proof-of-concept test chip integrating a 2.4GHz Integer-N synthesizer is designed and fabricated in the TSMC 0.25mum mixed-signal CMOS process. Simulations using time contraction show that the synthesizer switches 14% faster in the four-step mode compared to the one-step mode for a frequency step of 20MHz and 0.1% error tolerance.
DOI
https://doi.org/10.31274/rtd-180813-10948
Publisher
Digital Repository @ Iowa State University, http://lib.dr.iastate.edu
Copyright Owner
Sreenath Thoka
Copyright Date
2006
Language
en
Proquest ID
AAI1439926
File Format
application/pdf
File Size
73 pages
Recommended Citation
Thoka, Sreenath, "A 2.4GHz fast-switching integer-N frequency synthesizer " (2006). Retrospective Theses and Dissertations. 894.
https://lib.dr.iastate.edu/rtd/894