High speed data converter techniques

Thumbnail Image
Date
2000-01-01
Authors
Yu, Baiying
Major Professor
Advisor
William C. Black, Jr.
Committee Member
Journal Title
Journal ISSN
Volume Title
Publisher
Altmetrics
Authors
Research Projects
Organizational Units
Organizational Unit
Electrical and Computer Engineering

The Department of Electrical and Computer Engineering (ECpE) contains two focuses. The focus on Electrical Engineering teaches students in the fields of control systems, electromagnetics and non-destructive evaluation, microelectronics, electric power & energy systems, and the like. The Computer Engineering focus teaches in the fields of software systems, embedded systems, networking, information security, computer architecture, etc.

History
The Department of Electrical Engineering was formed in 1909 from the division of the Department of Physics and Electrical Engineering. In 1985 its name changed to Department of Electrical Engineering and Computer Engineering. In 1995 it became the Department of Electrical and Computer Engineering.

Dates of Existence
1909-present

Historical Names

  • Department of Electrical Engineering (1909-1985)
  • Department of Electrical Engineering and Computer Engineering (1985-1995)

Related Units

Journal Issue
Is Version Of
Versions
Series
Department
Electrical and Computer Engineering
Abstract

Moore's law not only applies to the semiconductor technology, it also applies to the Hard Disk Drive (HDD) system in the last 35 years. In order to meet the emerging demands of high performance computing application, HDD will continue to evolve in a very rapid pace. Very high speed analog-to-digital converters are demanded for Hard Disk Drive application.;FLASH architecture provides the highest speed using 2n-1 comparators to perform an n-bit conversion. In the extremes of speed, however, exotic technologies must still be used to achieve conversion rates beyond those obtained with a conventional silicon implementation. In this research, a four-way, time-interleaved flash ADC is demonstrated to achieve conversion speed up to 900MS/s using a 2.5v digital 0.25 micron bulk CMOS process. The maximum conversion rate practical with any technology is extended by the use of an array of well-matched flash ADCs. This technique trades off increased die area for increased speed in nearly one for one relationship but an reduced performance if the ADCs are not well matched in terms of gain, offset, nonlinearities and sampling skew. In the approach considered here, these problems are minimized by use of a simple method that ensures the individual ADC gain, offset and nonlinearities characteristics are inherently almost identical. A simple four phase clock generator is demonstrated which introduces only a small sampling skew. This scheme has been demonstrated in the comparatively simple 6-bit flash ADC case which achieved the highest acquisition speed of 900MS/s. Compared with the prior works, our work achieves higher SNDR at much higher analog input frequency at sampling frequency of 900MS/s. This same scheme may be applied to the first n-bits of a pipeline converter (or other converter method) enabling the same identical performance in the most significant bits.;In the second part of this dissertation, a new calibration principle with Voltage Controlled Resistors (VCR) for matched current sources is proposed. This technique can be used to produce multi copies of current units. Therefore, it is suitable for the calibration of high-resolution digital-to-analog converters that are based on equal current sources.

Comments
Description
Keywords
Citation
Source
Subject Categories
Copyright
Sat Jan 01 00:00:00 UTC 2000